IITB RISC
16-bit RISC Processor in Quartus using VHDL
Course projects for EE 309 (Microprocessors) and CS 683 (Advanced Computer Architecture)
Guide: Prof. Virendra Singh
- Devised an efficient 29 state FSM for an 8 register multicycle processor with a reduced instructionset, capable of performing 17 instructions involving arithmetic, branch, and memory read/write.
- Improved the processor by designing a 6-stage pipeline, optimized with hazard mitigation techniques.
- Synthesized in Quartus Prime using VHDL and later extended it by designing a 2-way fetch out-of-order superscalar processor with register renaming, ROB, and a 2-bit branch predictor.